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<!@TC:1732004095>

Copyright (C) 1994-2023 Synopsys, Inc.
This Synopsys software and all associated documentation are proprietary to Synopsys, Inc.
and may only be used pursuant to the terms and conditions of a written license agreement
with Synopsys, Inc. All other use, reproduction, modification, or distribution of the
Synopsys software or the associated documentation is strictly prohibited.
Tool: Synplify Pro (R)
Build: V-2023.09L-2
Install: C:\ToolSoftware\Diamond\3.14\synpbase
OS: Windows 10 or later
Hostname: DESKTOP-LK1D0PP

Implementation : MXO2_2000HC

# Written on Tue Nov 19 16:15:00 2024

##### DESIGN INFO #######################################################

Top View:                "Top"
Constraint File(s):      (none)




##### SUMMARY ############################################################

Found 0 issues in 0 out of 0 constraints


##### DETAILS ############################################################



Clock Relationships
*******************

Starting                                  Ending                                    |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise                     
-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
System                                    System                                    |     10.000           |     No paths         |     No paths         |     No paths                         
System                                    Top|Clk                                   |     10.000           |     No paths         |     No paths         |     No paths                         
Top|Clk                                   Top|Clk                                   |     10.000           |     No paths         |     No paths         |     No paths                         
Top|Clk                                   Top|FSMC_NWE                              |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk                                   Top|FSMC_NADV                             |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk                                   Top|Clk_Count_derived_clock[16]           |     10.000           |     No paths         |     No paths         |     No paths                         
Top|FSMC_NWE                              System                                    |     10.000           |     No paths         |     No paths         |     No paths                         
Top|FSMC_NWE                              Top|Clk                                   |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|FSMC_NWE                              Top|FSMC_NWE                              |     10.000           |     No paths         |     No paths         |     No paths                         
Top|FSMC_NWE                              Top|FSMC_NADV                             |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|FSMC_NWE                              LaserPulse|Clk_10ms_derived_clock[17]     |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|FSMC_NADV                             Top|FSMC_NWE                              |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|FSMC_NADV                             Top|FSMC_NADV                             |     10.000           |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[13]           Top|FSMC_NWE                              |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[13]           Top|FSMC_NADV                             |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[13]           Top|Clk_Count_derived_clock[13]           |     10.000           |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[16]           Top|Clk                                   |     10.000           |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[16]           Top|FSMC_NWE                              |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[16]           Top|FSMC_NADV                             |     Diff grp         |     No paths         |     No paths         |     No paths                         
Top|Clk_Count_derived_clock[16]           Top|Clk_Count_derived_clock[16]           |     10.000           |     No paths         |     No paths         |     No paths                         
LaserPulse|Clk_10ms_derived_clock[17]     Top|Clk                                   |     10.000           |     No paths         |     No paths         |     No paths                         
LaserPulse|Clk_10ms_derived_clock[17]     LaserPulse|Clk_10ms_derived_clock[17]     |     10.000           |     No paths         |     No paths         |     No paths                         
===============================================================================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.


<a name=UnconstrainedStartEndPointsCCK57></a>Unconstrained Start/End Points</a>
******************************

p:Cross_EN
p:EN1
p:EN2
p:EN3
p:EN4
p:FSMC_AD[0] (bidir end point)
p:FSMC_AD[0] (bidir start point)
p:FSMC_AD[1] (bidir end point)
p:FSMC_AD[1] (bidir start point)
p:FSMC_AD[2] (bidir end point)
p:FSMC_AD[2] (bidir start point)
p:FSMC_AD[3] (bidir end point)
p:FSMC_AD[3] (bidir start point)
p:FSMC_AD[4] (bidir end point)
p:FSMC_AD[4] (bidir start point)
p:FSMC_AD[5] (bidir end point)
p:FSMC_AD[5] (bidir start point)
p:FSMC_AD[6] (bidir end point)
p:FSMC_AD[6] (bidir start point)
p:FSMC_AD[7] (bidir end point)
p:FSMC_AD[7] (bidir start point)
p:FSMC_AD[8] (bidir end point)
p:FSMC_AD[8] (bidir start point)
p:FSMC_AD[9] (bidir end point)
p:FSMC_AD[9] (bidir start point)
p:FSMC_AD[10] (bidir end point)
p:FSMC_AD[10] (bidir start point)
p:FSMC_AD[11] (bidir end point)
p:FSMC_AD[11] (bidir start point)
p:FSMC_AD[12] (bidir end point)
p:FSMC_AD[12] (bidir start point)
p:FSMC_AD[13] (bidir end point)
p:FSMC_AD[13] (bidir start point)
p:FSMC_AD[14] (bidir end point)
p:FSMC_AD[14] (bidir start point)
p:FSMC_AD[15] (bidir end point)
p:FSMC_AD[15] (bidir start point)
p:FSMC_CLK
p:FSMC_NE
p:FSMC_NOE
p:FSMC_NWAIT
p:Key_in[0]
p:Key_in[1]
p:Key_in[2]
p:Key_in[3]
p:Key_in[4]
p:Key_in[5]
p:LED[0]
p:LED[1]
p:LaserLed
p:PulseOutCheck
p:PulseOut_48
p:PulseOut_49
p:RX1
p:RX2
p:RX3
p:RX4
p:RX6
p:TB_in
p:TX1
p:TX2
p:TX3
p:TX4
p:TX6
p:USART1_RX
p:USART1_TX
p:USART3_RX
p:USART3_TX
p:test1535_pin


<a name=InapplicableconstraintsCCK58></a>Inapplicable constraints</a>
************************

(none)


<a name=ApplicableConstraintsWithIssuesCCK59></a>Applicable constraints with issues</a>
**********************************

(none)


<a name=ConstraintsWithMatchingWildcardExpressionsCCK60></a>Constraints with matching wildcard expressions</a>
**********************************************

(none)


<a name=LibraryReportCCK61></a>Library Report</a>
**************


# End of Constraint Checker Report

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